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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14508B Dual 4-Bit Latch
The MC14508B dual 4-bit latch is constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. The part consists of two identical, independent 4-bit latches with separate Strobe (ST) and Master Reset (MR) controls. Separate Disable inputs force the outputs to a high impedance state and allow the devices to be used in time sharing bus line applications. These complementary MOS latches find primary use in buffer storage, holding register, or general digital logic functions where low power dissipation and/or high noise immunity is desired. * 3-State Output * Supply Voltage Range = 3.0 Vdc to 18 Vdc * Capable-of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load over the Rated Temperature Range MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol Parameter VDD Vin, Vout Iin, Iout PD Tstg DC Supply Voltage Value L SUFFIX CERAMIC CASE 623
P SUFFIX PLASTIC CASE 709
DW SUFFIX SOIC CASE 751E
IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII
Unit V V - 0.5 to + 18.0 10 500 - 65 to + 150 Input or Output Voltage (DC or Transient) - 0.5 to VDD + 0.5 Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature mA mW
ORDERING INFORMATION
MC14XXXBCP MC14XXXBCL MC14XXXBDW Plastic Ceramic SOIC
TA = - 55 to 125C for all packages.
_C
1 2 3 4 6 8 10
BLOCK DIAGRAM
MR ST DIS D0 D1 D2 D3 Q0 Q1 Q2 Q3 5 7 9 11
TL Lead Temperature (8-Second Soldering) 260 _C * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: - 12 mW/_C From 100_C To 125_C
TRUTH TABLE
MR 0 0 0 0 0 0 1 X ST 1 1 1 1 1 0 X X Disable 0 0 0 0 0 0 0 1 D3 0 0 0 0 1 X X X D2 0 0 0 1 0 X X X D1 0 0 1 0 0 X X X D0 0 1 0 0 0 X X X 0 Q3 0 0 0 0 1 Q2 0 0 0 1 0 Q1 0 0 1 0 0 Q0 0 1 0 0 0
Latched 0 0 0 High Impedance
13 14 15 16 18 20 22
MR ST DIS D0 D1 D2 D3
Q0 Q1 Q2 Q3
17 19 21 23
X = Don't Care
CIRCUIT DIAGRAM
DIS MR ST
VDD = PIN 24 VSS = PIN 12 VDD
Dn
Qn
(TO OTHER THREE LATCHES) VSS
REV 3 1/94
(c)MC14508B 1995 Motorola, Inc. 344
MOTOROLA CMOS LOGIC DATA
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source 5.0 5.0 10 15 IOL 5.0 10 15 15 -- 5.0 10 15 5.0 10 15 - 3.0 - 0.64 - 1.6 - 4.2 0.64 1.6 4.2 -- -- -- -- -- -- -- -- -- -- -- -- 0.1 -- 5.0 10 20 - 2.4 - 0.51 - 1.3 - 3.4 0.51 1.3 3.4 -- -- -- -- -- - 4.2 - 0.88 - 2.25 - 8.8 0.88 2.25 8.8 0.00001 5.0 0.005 0.010 0.015 -- -- -- -- -- -- -- 0.1 7.5 5.0 10 20 - 1.7 - 0.36 - 0.9 - 2.4 0.36 0.9 2.4 -- -- -- -- -- -- -- -- -- -- -- -- 1.0 -- 150 300 600 mAdc 3.5 7.0 11 -- -- -- 3.5 7.0 11 2.75 5.50 8.25 -- -- -- 3.5 7.0 11 -- -- -- mAdc Min -- -- -- - 55_C 25_C 125_C Max Min -- -- -- Typ # 0 0 0 Max Min -- -- -- Max Unit Vdc Output Voltage Vin = VDD or 0 "0" Level 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 Vdc "1" Level Vin = 0 or VDD Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) Total Supply Current** (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) Three-State Leakage Current VIL -- -- -- -- -- -- 2.25 4.50 6.75 -- -- -- VOH 4.95 9.95 14.95 4.95 9.95 14.95 5.0 10 15 4.95 9.95 14.95 Vdc Vdc Sink Iin Cin IDD Adc pF Adc IT IT = (1.46 A/kHz) f + IDD IT = (2.91 A/kHz) f + IDD IT = (4.37 A/kHz) f + IDD Adc ITL 15 -- 0.1 -- 0.0001 0.1 -- 3.0 Adc #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only at 25_C. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.008. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
MOTOROLA CMOS LOGIC DATA
MC14508B 345
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic All Types Typ # 100 50 40 220 90 60 100 50 35 - 15 0 0 70 35 20 25 10 5.0 20 10 10 55 35 30 75 40 35 80 35 30 105 50 35 Symbol VDD 5.0 10 15 tPLH, tPHL 5.0 10 15 tWH(R) 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 tPLZ 5.0 10 15 5.0 10 15 5.0 10 15 -- -- -- 200 100 70 30 25 20 140 70 40 50 20 10 50 35 35 -- -- -- -- -- -- -- -- -- -- -- -- 440 180 120 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 170 100 70 170 100 70 170 100 70 210 100 70 ns Min -- -- -- Max 200 100 80 ns Unit ns Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns Propagation Delay Time, Dn or MR to Q tPLH, tPHL = (1.7 ns/pF) CL + 135 ns tPLH, tPHL = (0.66 ns/pF) CL + 57 ns tPLH, tPHL = (0.5 ns/pF) CL + 35 ns Master Reset Pulse Width tTLH, tTHL Master Reset Removal Time trem ns Strobe Pulse Width tWH(S) ns Setup Time Data to Strobe Hold Time Strobe to Data 3-State Propagation Delay Time Output "1" to High Impedance tsu ns th ns tPHZ ns Output "0" to High Impedance High Impedance to "1" Level tPZH High Impedance to "0" Level tPZL * The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
PIN ASSIGNMENT
MRA STA DISA D0A Q0A D1A Q1A D2A Q2A D3A Q3A VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD Q3B D3B Q2B D2B Q1B D1B Q0B D0B DISB STB MRB
MC14508B 346
MOTOROLA CMOS LOGIC DATA
tWH(S) STROBE INPUT tsu th Dn INPUT tPLH Qn OUTPUT 10% tTLH 90% 50% tTHL 50% tPHL MASTER RESET INPUT Qn OUTPUT VOL 50% 50% tWH(R) 50% VSS VOH VDD
Figure 1. AC Waveforms
VDD VDD ST1 1.0 k
PULSE GENERATOR VDD ST3
MR ST DISABLE D0 D1 D2 D3
Q0 Q1 Q2 Q3 1.0 k
Test tPHZ tPLZ tPZL tPZH
ST1 Open Close Close Open
ST2 Close Open Open Close
ST3 Close Open Open Close
ST4 Open Close Close Open
ST4
VSS
CL
ST2
20 ns 50% DISABLE tPLZ 10% Q3 OUTPUT tPHZ 90% 10% 90%
20 ns VDD 10% tPZL 90% VSS VOH 2.5 V @ VDD = 5 V, 10 V, AND 15 V 2 V @ VDD = 5 V 6 V @ VDD = 10 V 10 V @ VDD = 15 V VOL
tPZH
Figure 2. 3-State AC Test Circuit and Waveforms
MOTOROLA CMOS LOGIC DATA
MC14508B 347
3-STATE MODE OF OPERATION
The MC14508B can be used in bussed systems as shown. The output terminals of N 4-bit latches can be directly wired to a bus line, and to one of the 4-bit latches selected. The selected latch controls the logic state of the bus line and the remaining (N-1) 4-bit latches are disabled into a high impedance "off" state. The number of latches, N, which may be connected to a bus line is determined from the output drive current, IOD, the 3-state or disabled output leakage current, ITL, and the load current, IL, required to drive the bus line (including fanout to other device inputs) and can be calculated by the following: IOD - IL N= +1 ITL N must be calculated for both high and low logic states of the bus line.
1/2 DISABLED MC14508B SELECTED AS 1/2 DRIVING DEVICE MC14508B
IOD
IOD ITL 1/2 DISABLED MC14508B
ITL ITL
ITL
IL IL BUS LINES
TYPICAL 3-STATE APPLICATIONS
EXAMPLE 1
RESET CLOCK MC14015B SERIAL DATA STROBE MC QUAD LATCH 14508B (3-STATE) QUAD LATCH (3-STATE) 4-BIT SHIFT REGISTER 4-BIT SHIFT REGISTER
DISABLE DISABLE
4-LINE DATA BUS
EXAMPLE 2
DATA BUS 3-STATE 4-BIT LATCH MC 14508B 4-LINE DATA BUS 4-LINE DATA BUS MC14519B A B 3-STATE 4-BIT LATCH 3-STATE 4-BIT LATCH 3-STATE 4-BIT LATCH MC 14508B
MC14508B 348
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 623-05 ISSUE M
24 13 NOTES: 1. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 2. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION (WHEN FORMED PARALLEL). DIM A B C D F G J K L M N MILLIMETERS MIN MAX 31.24 32.77 12.70 15.49 4.06 5.59 0.41 0.51 1.27 1.52 2.54 BSC 0.20 0.30 3.18 4.06 15.24 BSC 0_ 15 _ 0.51 1.27 INCHES MIN MAX 1.230 1.290 0.500 0.610 0.160 0.220 0.016 0.020 0.050 0.060 0.100 BSC 0.008 0.012 0.125 0.160 0.600 BSC 0_ 15_ 0.020 0.050
B
1 12
A
SEATING PLANE
F
C
L G D N K M J
P SUFFIX PLASTIC DIP PACKAGE CASE 709-02 ISSUE C
24 13 NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 31.37 32.13 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.03 0.20 0.38 2.92 3.43 15.24 BSC 0_ 15_ 0.51 1.02 INCHES MIN MAX 1.235 1.265 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.080 0.008 0.015 0.115 0.135 0.600 BSC 0_ 15_ 0.020 0.040
B
1 12
A N K H G F D
SEATING PLANE
C
L
M
J
MOTOROLA CMOS LOGIC DATA
MC14508B 349
OUTLINE DIMENSIONS
DW SUFFIX PLASTIC SOIC PACKAGE CASE 751E-04 ISSUE E
-A-
24 13 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0_ 8_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0_ 8_ 0.395 0.415 0.010 0.029
-B-
12X
P 0.010 (0.25)
M
B
M
1
12
24X
D 0.010 (0.25)
M
J TA
S
B
S
F R C -T-
SEATING PLANE X 45 _
M
22X
G
K
DIM A B C D F G J K M P R
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MC14508B 350
*MC14508B/D*
MOTOROLA CMOS LOGIC DATA MC14508B/D

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